1. Field of the Invention
The present invention relates to a PCI, and more particularly, to device and method for controlling a PCI ethernet which is adapted to keep already received data in place when priority is shifted to some other device in the middle of data reception, and continuing reception of the data starting from data following the received data when the priority comes back, for minimizing a time period required for data transmission.
2. Discussion of the Related Art
A related art device and method for controlling a PCI ethernet will be explained with reference to the attached drawings. FIG. 1 illustrates a block diagram of a background art adapter for use in data communications between a host computer and various media.
Referring to FIG. 1, the related art adapter 10 is provided with a twist pair network cable 30, a twist pair transceiver part 100, an attachment unit interface part 110, a decoder part 115, an encoder part 120, a receive controlling part 130, a transmit controlling part 140, an ethernet controlling part 150, an FIFO(First In First Out) transmit part 180, an FIFO receive part 160, a receiver side RAM FIFO part 170, transmission side RAM FIFO part 180, and a host interface part 200. The twist pair transceiver part 100 is connected between the attachment unit interface part 110, and decoder part 115 and encoder part 120 in parallel. The decoder part 115 is connected to the receive controlling part 130, and the encoder part 120 is connected to the transmit controlling part 140. The receive controlling part 130 and the transmit controlling part 140 are connected to each other and have the ethernet controlling part 150 in common. The receive controlling part 130 is connected to the FIFO transmit part 180 connected to the transmission side RAM FIFO part 190. The transmit controlling part 180 is connected to the FIFO transmit part 180 connected to the transmission side RAM FIFO part 190. Both the FIFO transmit part 180 and the FIFO receive part 160 are connected to the host interface part 200. The part enclosed by a dotted line, including all the different controlling parts, RAMs, tranceiver parts, is called as an ASIC(Application Specific Integrated Circuit) part 210. The ASIC part 210 has an EEPROM 220 connected to the host interface part 200 providing data locations such as addresses of media or stations, a clock part 240 and a network management part 250 for managing signals according to various network states. The decoder part 115 and the encoder part 120 are connected to a VCO (Voltage Controlled Oscillator) 270. The unexplained reference numeral 230 is a boot PROM.
The operation of the aforementioned background art adapter will be explained with reference to FIG. 2.
In general, all the data transmission between the adapter 10 and the host computer are conducted by a program input/output device PIO. Data transmitted from the host computer is stored in the transmission side FIFO part 420 in the form of 2 word (4 bytes) by the adapter 10. That is, as shown in FIG. 2, transmission data to be transmitted from the host computer to each ethernet computer are stored in the transmission side RAM FIFO part 190 by a driver. In this instance, an amount of data in the transmission side RAM FIFO part 190 and a threshold value are compared(420), to start data transmission(425) if the amount of data is greater than the threshold value even if the data does not compose one perfect packet unit. The data transmission is conducted until one complete packet is transmitted as long as no error occurs. During data transmission, the error detecting part detects any occurrence of error (430), and, if an error occurs, determines if the error is an underrun error (435). And, if the error is determined to be an underrun error, a xe2x80x9cbadxe2x80x9d CRC is generated (440). In the case when the error is not an underrun error, or the xe2x80x9cbadxe2x80x9d CRC was generated, a status bit that informs of error occurrence in the middle of data transmission is updated(445), and data transmission is stopped(450). In this instance, as data transmission is stopped on determination of the error being an underrun error, on restarting of data transmission, the FIFO transmit part 180 should request that the host computer transmit the data from the beginning. Accordingly, the host computer transmits data to the transmission side RAM FIFO part 190 as the FIFO transmit part 180 requests. The data transmission is continued as discussed. In the meantime, if the error detecting part detects no error, a transmission status bit is updated (460). Then, whether there has been transmission of one complete packet of data is determined (465). If the one complete packet of data is not transmitted fully, the process proceeds to the first step(420) for transmission of the remaining data required for completion of one complete packet. If the one complete packet of data is transmitted fully, an interrupt communicating this to a driver is provided(470). Thus, data can be transmitted from the host computer to each ethernet computer.
However, the controlling method of the related art PCI ethernet controlling device has the following problems.
On occurrence of an underrun in the middle of data transmission, all the packet data in the transmission side RAM FIFO part up to the present time is abandoned, and data storage in the transmission side RAM FIFO starts from the beginning. Therefore, as the driver requests from the host computer transmission of the data from the beginning, storage of the data in the RAM FIFO part if the data is available, and transmit the data again, a transmission time for transmission of data is delayed accordingly.
Accordingly, the present invention is directed to a device and method for controlling a PCI ethernet that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a device and method for controlling a PCI ethernet which can shorten data transmission time.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the device for controlling a PCI ethernet for transmission of data between a host computer and various media includes a RAM FIFO part for storing data transmitted from the host computer and providing the data in succession when an amount of stored data becomes greater than a transmission threshold value, a first controlling part for controlling data storage in the RAM FIFO part and comparing the amount of stored data to the threshold value for providing a data start signal, and a second controlling part for reading data in succession in response to the data start signal from the first controlling part and updating the position of a temporary sink pointer which marks the amount of data read upon occurrence of an underrun, to a position in the RAM FIFO part at which the data is stored.
In another aspect of the present invention, there is provided a method for controlling a PCI ethernet controlling device for data transmission between a host computer and various media, including the steps of (1) storing data to be transmitted in a memory in succession until an amount of the data becomes greater than a threshold value when the data is transmitted in succession, (2) retaining the data already stored in memory while storing new data in the memory starting from data which is not yet stored in memory if an underrun occurs in the middle of data transmission, and storing data in the memory from beginning of the data if an error other than underrun occurs, and (3) determining completion of transmission of one full packet of data if no error occurs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.